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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document from Analog Marketing: MC33887/D Rev 2, 08/2002 Preliminary Information 6.0 A H-Bridge with Enable The 33887 is a monolithic H-Bridge with a Sleep Mode feature ideal for fractional horsepower DC-motor and bi-directional thrust solenoid control. The IC incorporates internal control logic, charge pump, gate drive, and low RDS(ON) MOSFET output circuitry. The 33887 is able to control continuous inductive DC load currents of 6.0 A. Output loads can be Pulse Width Modulation (PWM) controlled at frequencies to 10 kHz. An internal output current monitoring circuit provides a proportional (1/375th) feedback current output for the microcontroller to monitor the output current and provide closedloop control. A Fault Status output reports undervoltage, overcurrent, and overtemperature conditions. Two independent inputs provide polarity control of two half-bridge totem-pole outputs. Two disable inputs force the H-Bridge outputs to tristate (exhibit high impedance). The 33887 is parametrically specified over a temperature range of -40C TA 125C, 5.0 V VPWR 28 V, and is available in three different surface mount packages. Features * 5.0 V to 36 V Operation * 120 m RDS(ON) H-Bridge Switches * TTL/CMOS Compatible Inputs * PWM Frequencies to 10 kHz * Automatic PWM Overcurrent Limiting * Output Short Circuit Protection * Overtemperature Output Current Reduction with Shutdown * Undervoltage Shutdown * Fault Status Reporting * High-Side Current Feedback Output Provides Real-Time Current Monitoring 33887 6.0 A H-BRIDGE WITH ENABLE DH SUFFIX 20-LEAD HSOP CASE 979C FC SUFFIX 44-LEAD QFN CASE 1310 DWB SUFFIX 54-LEAD SOIC-EP CASE 1377 PIN CONNECTIONS HSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AGND FS IN1 VPWR VPWR OUT1 OUT1 FB PGND PGND PGND PGND D2 OUT2 OUT2 VPWR CCP D1 IN2 EN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 QFN FB PGND PGND PGND PGND PGND PGND PGND PGND D2 OUT2 OUT2 NC NC NC NC OUT2 OUT2 VPWR 23 24 25 26 27 28 IN2 EN NC NC VPWR VPWR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SOIC PGND PGND PGND PGND NC NC NC D2 NC OUT2 OUT2 OUT2 OUT2 NC VPWR 28 29 30 31 32 33 34 35 36 37 NC NC AGND FS IN1 NC NC NC NC VPWR 29 VPWR 30 VPWR 31 32 33 34 35 36 38 39 40 41 42 43 44 NC NC AGND FS IN1 VPWR OUT1 OUT1 NC OUT1 OUT1 NC NC 38 VPWR 39 VPWR 40 VPWR 41 42 43 44 45 46 47 48 49 50 51 52 53 54 NC OUT1 OUT1 OUT1 OUT1 NC FB NC NC NC PGND PGND PGND PGND 37 VPWR 16 VPWR 17 VPWR 18 VPWR 19 20 21 22 23 24 25 26 27 NC NC NC NC CCP D1 IN2 EN NC 20 VPWR 21 CCP 22 D1 33887 Simplified Application Diagram VPWR 5.0 V CCP FS EN IN1 IN2 D1 D2 FB VPWR OUT1 ORDERING INFORMATION Motor OUT2 GND Device PC33887DH/R2 PC33887FC/R2 PC33887DWB/R2 Temperature Range (TA) -40 to 125C -40 to 125C -40 to 125C Package 20 HSOP 44 QFN 54 SOIC-EP MCU or DSP This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc. 2002 CCP Charge Pump VPWR 80 uA (each) 5.0 V Regulator Current Limit, Overcurrent Sense, & Feedback Circuit OUT1 Gate Drive OUT2 Over Temperature Undervoltage IN1 IN2 D1 D2 25 uA FS FB Control Logic AGND PGND Figure 1. 33887 Internal Block Diagram PIN FUNCTION DESCRIPTION HSOP 1 2 QFN 33 34 SOIC 30 31 Pin Name AGND FS Description Low current Analog signal ground. Open drain active LOW Fault Status output requiring a pull-up resistor to 5.0 V. True Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH). Positive power source connection. H-Bridge output 1. Current sensing feedback output providing ground referenced 1/375th (0.00266) of H-Bridge high-side output current. Device high current power ground. 3 4, 5, 16 6, 7 8 35 19, 20, 27-30 38, 39, 41, 42 1 32 15-18, 37-40 42-45 47 IN1 VPWR OUT1 FB 9-12 2-9, 36, 37 10 1-4, 51-54 8 PGND 13 D2 Active LOW input used to simultaneously tristate disable both H-Bridge outputs. When D2 is Logic LOW, both outputs are tristate. H-Bridge output 2. External reservoir capacitor connection for internal Charge Pump. Active HIGH input used to simultaneously tristate disable both H-Bridge outputs. When D1 is Logic HIGH, both outputs are tristate. True Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH). True Logic input Enable control of device (i.e., EN logic High = Full Operation, EN logic LOW = Sleep Mode). No internal connection to this pin. 14, 15 17 18 11, 12, 17, 18 21 22 10-13 23 24 OUT2 CCP D1 19 20 23 24 25 26 IN2 EN - 13-16, 25, 26, 31, 32, 40, 43, 44 5-7, 9, 14, 19-22, 27-29, 33-36, 41, 46, 48-50 NC 33887 2 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Power Supply Voltage Normal Operation (Steady-State) Transient (Note 1) Input Voltage (Note 2) FS Status Output (Note 3) Continuous Output Current (Note 4) ESD Voltage Human Body Model (Note 5) Machine Model (Note 6) Storage Temperature Ambient Temperature (Note 7) Operating Junction Temperature Lead Soldering Temperature (Note 8) Approximate Junction-to-Board Thermal Resistance (Note 9) HSOP QFN SO-EP Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. VESD1 VESD2 TSTG TA TJ TSOLDER RJ-B ~5.0 ~18 ~12 C/W TBD 200 -65 to 150 -40 to 125 -40 to 150 260 C C C C V Symbol Value 36 40 7.0 7.0 6.0 V V A Unit VPWR(SS) VPWR(t) VIN V FS IOUT(CONT) V Device will survive the transient overvoltage indicated for a maximum duration of 500 ms. Exceeding the input voltage on IN1, IN2, EN, D1, or D2 may cause a malfunction or permanent damage to the device. Exceeding the pull-up resistor voltage on the open Drain FS pin may cause permanent damage to the device. Continuous output current capability so long as junction temperature is 150C. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). ESD2 testing is performed in accordance with the Machine Model (CZAP = 100 pF, RZAP = 0 ). The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking. Lead soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Exposed heat sink pad plus the power and ground terminals comprise the main heat conduction paths. The actual RJ-B (junction-to-PC board) values will vary depending on solder thickness and composition and copper trace. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 3 STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 5.0 V VPWR 28 V and -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit Power Supply Operating Voltage Range (Note 10) Steady-State Transient (t < 500 ms) (Note 11) Sleep State Supply Current (Note 12) VEN = 0 V, ILOUT = 0 A Standby Supply Current ILOUT = 0 A, VEN = 5.0 V Threshold Supply Voltage Switch-OFF Switch-ON Hysteresis VPWR(thres-OFF) VPWR(thres-ON) VPWR(hys) 4.15 4.5 150 4.4 4.75 - 4.65 5.0 - V V mV IPWR(standby) - - 20 mA VPWR(SS) VPWR(t) IPWR(sleep) - 25 50 A 5.0 - - - 36 40 V V Charge Pump Charge Pump Voltage VPWR = 4.15 V VPWR < 40 V Control Inputs Input Voltage (IN1, IN2, D1, D2) Threshold HIGH Threshold LOW Hysteresis Input Current (IN1, IN2, D1) VIN - 0.0 V Input Current (D2, EN) V D2 = 5.0 V VCP - VPWR 3.35 - - - - 20 V V VIH VIL VHYS IIN 3.5 - 0.7 - - 1.0 - 1.4 - V V V -200 -80 - A I D2 - 25 100 A Notes: 10. Parameter is guaranteed by design but not production tested. 11. Device will survive the transient overvoltage indicated for a maximum duration of 500 ms. 12. IPWR(sleep) is with sleep mode function Enabled. 33887 4 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 5.0 V VPWR 28 V and -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit Power Outputs (OUT1, OUT2) Output-ON Resistance (Note 13) 5.0 V < VPWR < 28 V, TJ = 25C 8.0 V < VPWR < 28 V, TJ = 150C 5.0 V < VPWR < 8.0 V, TJ = 150C Output Latch-OFF Current Output Latch-OFF Time Output Blanking Time High-Side Overcurrent Detection Low-Side Overcurrent Detection Leakage Current (Note 14) VOUT = VPWR VOUT = GND Free-Wheeling Diode Forward Voltage Drop (Note 15) IOUT = 3.0 A Free-Wheeling Diode Reverse Recovery Time (Note 15) Switch-OFF Thermal Shutdown Hysteresis TLIM THYS 175 10 - - - 30 C C trr VF - 100 - - 2.0 - V ns ILATCH-OFF ta tb IOCD(H) IOCD(L) IOUT(leak) - - 100 30 200 60 A A ROUT - - - 6.0 15 12 11 9.0 120 - - 7.0 20.5 16.5 - - - 225 300 8.5 26 21 - - m m m A s s A A Notes: 13. Output-ON resistance as measured from output to VPWR and GND. 14. 15. Outputs switched OFF with D1 or D2. Parameter is guaranteed by design but not production tested. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 5 STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 5.0 V VPWR 28 V and -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit High-Side Current Sense Feedback Feedback Current I LOAD = 0 mA I LOAD = 500 mA I LOAD = 1.5 A I LOAD = 3.0 A I LOAD = 6.0 A I FB - 1.07 3.6 7.2 14.4 - -1.33 4.0 8.0 16.0 600 1.60 4.4 8.8 17.6 A mA mA mA mA Fault Status (Note 16) Fault Status Leakage Current (Note 17) V FS = 5.0 V Fault Status SET Voltage (Note 18) I FS = 300 A V FS(LOW) - - 1.0 V I FS(leak) - - 10 A Notes: 16. Fault Status output is an open Drain output requiring a pull-up resistor to 5.0 V. 17. Fault Status Leakage Current is measured with Fault Status HIGH and not SET. 18. Fault Status Set Voltage is measured with Fault Status LOW and SET with I FS = 300 A. 33887 6 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 5.0 V VPWR 28 V and -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit Timing Characteristics PWM Frequency (Note 19) Maximum Switching Frequency During Current Limit (Note 20) Output ON Delay (Note 21) fPWM fMAX td(ON) - td(OFF) - tf, tr 2.0 td(disable) tFAULT tpod - - - 5.0 - 4.0 1.0 8.0 8.0 - 5.0 s s s ms - 18 s - 18 s - - - - 10 20 kHz kHz VPWR = 14 V Output OFF Delay (Note 21) VPWR = 14 V Output Rise and Fall Time (Note 22) VPWR = 14 V, Iout = 3.0 A Disable Delay Time (Note 23) Over-Current/Temperature Turn-OFF Time (Note 24) Power-OFF Delay Time (Note 25) Notes: 19. The outputs can be PWM controlled from an external source. The PWM Frequency is the externally induced output switching frequency, the maximum frequency of which is limited by the internal charge pump. 20. The Maximum Switching Frequency during Current Limit is internally implemented. The internal control produces a constant OFF-time PWM of the output. The output load current effects the Maximum Switching Frequency. 21. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition direction) of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from the midpoint of the input signal to the 90% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from the midpoint of the input signal to the 10% point of the output response signal. See Figure 3. 22. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 4. 23. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tristate response. See Figure 3. 24. Increasing output currents will become limited at 6.5 A. Hard shorts will breach the 6.5 A limit, forcing the output into an immediate tristate latch-OFF. See Figure 5 and Figure 6. Output current limiting will cause junction temperatures to rise. A junction temperature above 160C will cause the output current limit to progressively "fold-back" or decrease to 2.5 A typical at 175C where thermal latch-OFF will occur. See Figure 7. 25. This parameter has been characterized but is not production tested. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 7 VIN1, IN2 (V) 5.0 50% 0 td(ON) 90% 50% td(OFF) VOUT1, 2 (V) VPWR 0 10% TIME Figure 2. Output Delay Time Figure 3. Disable Delay Time VOUT1, 2 (V) V PWR 90% tf tr 90% 10% 10% 0 Figure 4. Output Switching Time 33887 8 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA ILOAD, OUTPUT CURRENT (A) 8.0 6.5 Overcurrent (Minimum) PWM Current Limiting (See Figure 6.) 0 [1] IN1 OR [0] IN2 IN1 IN2 Hard Output Short Latch-OFF D1, LOGIC IN D2, LOGIC IN FS, FAULT STATUS IN, LOGIC IN [1] [0] [1] [0] [1] Outputs Operational (per Input Control Condition) [0] TIME Outputs Tristate Latched (H-Bridge Switches OFF) Figure 5. Output Load Current Limiting Versus Time ILOAD, OUTPUT CURRENT (A) 8.0 ta 6.5 tb Overcurrent Minimum Threshold ta = Tristate Output OFF Time tb = Current Limit Blank Time Typical PWM Load Current Limiting Waveform Hard Output Short Latch-OFF TIME Figure 6. PWM Current Limiting Detail MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 9 IMAX, OUTPUT CURRENT (A) 6.6 2.5 Thermal Shutdown 160 175 T J, JUNCTION TEMPERATURE (o C) Figure 7. Maximum Output Current Limiting Versus Temperature 33887 10 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Table 1. Truth Table The tristate conditions and the fault status are reset using D1 or D2. The truth table uses the following notations: L = Low, H = High, X = High or Low, and Z = High impedance (all output power transistors are switched off). Input Conditions Device State Status Outputs EN D1 D2 H H H H X L H H X Z X X X X X IN1 H L L H X X Z X X X X X X X X IN2 L H L H X X X Z X X X X X X X FS H H H H L L H H L L L L L H H OUT1 H L L H Z Z H X Z Z Z Z Z Z Z OUT2 L H L H Z Z X H Z Z Z Z Z Z Z Forward Reverse Free Wheeling Low Free Wheeling High Disable 1 (D1) Disable 2 (D2) IN1 Disconnected IN2 Disconnected D1 Disconnected D2 Disconnected Undervoltage (Note 26) Overtemperature (Note 27) Overcurrent (Note 27) Sleep Mode EN EN Disconnected H H H H H H H H H H H H H L Z L L L L H X L L Z X X X X X X Notes: 26. In the case of an undervoltage condition, the outputs tristate and the fault status is SET logic LOW. Upon undervoltage recovery, fault status is reset automatically or automatically cleared and the outputs are restored to their original operating condition. 27. When an overcurrent or overtemperature condition is detected, the power outputs are tristate latched-OFF independent of the input signals and the fault status flag is SET logic LOW. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 11 SYSTEM/APPLICATION INFORMATION INTRODUCTION Numerous protection and operational features (speed, torque, direction, dynamic breaking, PWM control, and closedloop control), in addition to the 6.0 A output current capability, make the 33887 a very attractive cost-effective solution for controlling a broad range of fractional horsepower DC-motors. A pair of 33887 devices can be used to control bipolar stepper motors in both directions. In addition, the 33887 can be used to control permanent magnet solenoids in a push-pull variable force fashion using PWM control. The 33887 can also be used to excite transformer primary windings with a switched square wave to produce secondary winding AC currents. As shown in Figure 1, Internal Block Diagram, the 33887 is a fully protected monolithic H-Bridge with Enable, Fault Status reporting, and High-Side current sense feedback to accommodate closed-loop PWM control. For a DC-motor to run the input conditions need be as follows: Enable input logic HIGH, D1 input logic LOW, D2 input logic HIGH, FS flag cleared (logic HIGH), with one IN logic LOW and the IN other logic HIGH to define output polarity. The 33887 can execute Dynamic Breaking by simultaneously turning-ON either the two HighSide or the two Low-Side H-Bridge switches; e.g., IN1 and IN2 logic HIGH or IN1 and IN2 logic LOW. The 33887 outputs are capable of providing a continuous DC load current of 6.0 A from a 36 V VPWR source. An internal charge pump supports PWM frequencies to 10 kHz. An external pull-up resistor is required for the open drain FS pin for fault status reporting. The 33887 has a current feedback output (FB) for "real time" monitoring of output current to facilitate closedloop operation for motor speed and torque control. Two independent inputs (IN1 and IN2) provide control of the two totem-pole half-bridge outputs. Two disable inputs (D1 and D2) are for forcing the H-Bridge outputs to a high impedance state (all H-Bridge switches OFF). An EN pin controls an enable function that allows the 33887 to be placed in a powerconserving sleep mode. The 33887 has Undervoltage Shutdown with automatic recovery, Output Current Limiting, Output Short-Circuit LatchOFF, and Overtemperature Latch-OFF. An Undervoltage Shutdown, Output Short-Circuit Latch-OFF, or Overtemperature Latch-OFF fault condition will cause the outputs to turn-OFF (tristate) and the fault output flag to be set LOW. Either of the D inputs or VPWR must be "toggled" to clear the fault flag. The Overcurrent/Overtemperature Shutdown scheme is unique and best described as using a junction temperature dependent output current "fold back" protection scheme. When an overcurrent condition is experienced, the current limited output is "ramped down" as the junction temperature increases above 160C, until at 175C the output current has decreased to about 2.5 A. Above 175C, the Overtemperature Shutdown (Latch-OFF) occurs. This feature allows the device to remain in operation for a longer time with unexpected loads, but with regressive output performance at junction temperatures above 160C. FUNCTIONAL PIN DESCRIPTION PGND and AGND Power and analog ground pins. The power and analog ground pins should be connected together with a very low impedance connection. VPWR VPWR pins are the power supply inputs to the device. All VPWR pins must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between pins. VPWR pins have an undervoltage threshold. If the supply voltage drops below a VPWR undervoltage threshold, the output power stage switches to a tristate condition and the fault status flag is SET and the Fault Status pin voltage switched to a logic LOW. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins and the fault status flag is automatically reset logic HIGH. Fault Status (FS) This pin is the device fault status output. This output is an active LOW open drain structure requiring a pull-up resistor to 5.0 V. Refer to Table 1, Truth Table. IN1, IN2, D1, D2 These pins are input control pins used to control the outputs. These pins are 5.0 V CMOS-compatible inputs with hysteresis. The IN1 and IN2 independently control OUT1 and OUT2, respectively. D1 and D2 are complimentary inputs used to tristate disable the H-Bridge outputs. When either D1 or D2 is SET (D1 = logic HIGH or D2 = logic LOW) in the disable state, outputs OUT1 and OUT2 are both tristate disabled; however, the rest of the device circuitry is fully operational and the supply IPWR(standby) current is reduced to a few milli-amperes. See Table 1, Truth Table, and STATIC ELECTRICAL CHARACTERISTICS (continued) table. OUT1, OUT2 These pins are the outputs of the H-Bridge with integrated free-wheeling diodes. The bridge output is controlled using the IN1, IN2, D1, and D2 inputs. The outputs have Pulse Width 33887 12 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Modulated (PWM) current limiting above 6.5 A. The outputs also have thermal shutdown (tristate latch-OFF) with hysteresis as well as short circuit latch-OFF protection. A disable timer (time tb) incorporated to detect currents that are higher than current limit is activated at each output activation to facilitate detecting hard output short conditions. See Figure 6. CCP I/O or an unpowered microcontroller, or the EN input becomes disconnected. FB The device has a feedback output (FB) for "real time" monitoring of H-Bridge high-side output currents to facilitate closed-loop operation for motor speed and torque control. The FB pin provides current sensing feedback of the HBridge high-side drivers. When running in the forward or reverse direction, a ground referenced 1/375th (0.00266) of load current is output to this pin. Through the use of an external resistor to ground, the proportional feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can "read" the current proportional voltage with its analog to digital converter (ADC). This is intended to provide the user with motor current feedback for motor torque control. The accuracy is 20% at load currents <1.5 A and 10% at load currents >1.5 A. If PWM-ing is implemented using the disable pin inputs (either D1 or D2), a small filter capacitor (<1.0 F) may be required in parallel with the external resistor to ground for fast spike suppression. Charge pump output pin. A filter capacitor (up to 33 nF) can be connected from the CCP pin and PGND. The device can operate without the external capacitor, although the CCP capacitor helps to reduce noise and allows the device to perform at maximum speed, timing, and PWM frequency. EN The EN pin is used to place the device in a sleep mode so as to consume very low currents. When the EN pin voltage is a logic LOW state, the device is in the sleep mode. The device is enabled and fully operational when the EN pin voltage is logic HIGH. An internal pull-down resistor maintains the device in sleep mode in the event EN is driven through a high impedance PERFORMANCE FEATURES Short Circuit or Overcurrent Protection If an output overcurrent condition is detected, the power outputs tristate latched-OFF independent of the input signal states and the fault status output flag is SET logic LOW. If the D1 voltage changes from logic HIGH to logic LOW or from logic LOW to logic HIGH on D2, the output switches ON again and the fault status flag is reset (cleared) to a logic HIGH state. The output stage will always switch into the mode defined by the input pins (IN1, IN2, D1, and D2), provided the device junction temperature is within the specified operating temperature. PWM Current Limiting The maximum current flow under normal operating conditions is limited to IMAX (6.0 to 8.5 A). When the maximum current value is reached, the output stages are tristated for a fixed time (ta) of 20 s typical. Depending on the time constant associated with the load characteristics, the output current decreases during the tristate duration until the next output ON cycle occurs. See Figure 6. The PWM current limitation value is dependent upon the device junction temperature. When -40C < TJ < 160C, IMAX is between 6.0 and 8.5 A. When TJ exceeds 160C, the IMAX current decreases linearly down to 2.5 A typical at 175C typical (or where the device reaches TLIM) and overtemperature shutdown occurs. See Figure 7. This feature allows the device to remain operational for a longer time but at a regressing output performance level at junction temperatures above 160C. Overtemperature Shutdown and Hysteresis If an overtemperature condition occurs, the power outputs are tristate latched-OFF independent of the input signals and the fault status flag is SET logic LOW. If the D1 voltage changes from logic HIGH to logic LOW or from logic LOW to logic HIGH on D2, the output stage switches ON again, providing the temperature is below the overtemperature threshold limit minus the hysteresis. The fault status flag is reset (cleared) logic HIGH. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 13 APPLICATIONS A typical application schematic is shown in Figure 8. For precision high-current applications in harsh, noisy environments, the VPWR by-pass capacitor may need to be substantially larger. +24 V 1.0 uF NC NC OUT1 OUT1 NC OUT1 OUT1 VPWR VPWR 1.0 uF 100 Motor OUT2 NC NC NC NC OUT2 OUT2 VPWR VPWR CCP 1 2 3 4 5 6 7 8 9 10 11 FB PGND PGND PGND PGND PGND PGND PGND PGND D2 OUT2 IN1 FS 44 43 42 41 40 39 38 37 36 35 34 33887FC AGND NC NC VPWR VPWR VPWR VPWR NC NC EN IN2 D1 33 32 31 30 29 28 27 26 25 24 23 1.0 uF 1.0 uF FS IN1 FB D2 D1 IN2 EN Figure 8. Typical Application Schematic 33887 14 12 13 14 15 16 17 18 19 20 21 22 1.0 uF 33 nF MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PACKAGE DIMENSIONS DH SUFFIX (20-LEAD HSOP) PLASTIC PACKAGE CASE 979C-02 ISSUE A PIN ONE ID h X 45 E2 1 20 E3 D e/2 D1 10 11 EXPOSED HEATSINK AREA NOTES: 1. CONTROLLING DIMENSION: MILLIMETER. 2. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.150 PER SIDE. DIMENSIONS D AND E1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE TIEBAR PROTRUSIONS. ALLOWABLE TIEBAR PROTRUSIONS ARE 0.150 PER SIDE. D2 18X B e E1 10X E A E4 BOTTOM VIEW MILLIMETERS DIM MIN MAX A 3.000 3.400 A1 0.100 0.300 A2 2.900 3.100 A3 0.00 0.100 D 15.800 16.000 D1 11.700 12.600 D2 0.900 1.100 E 13.950 14.450 E1 10.900 11.100 E2 2.500 2.700 E3 6.400 7.200 E4 2.700 2.900 L 0.840 1.100 L1 0.350 BSC b 0.400 0.520 b1 0.400 0.482 c 0.230 0.320 c1 0.230 0.280 e 1.270 BSC h --- 1.100 q 0 8 aaa 0.200 bbb 0.100 bbb M C B Y A A2 c C SEATING PLANE H DATUM PLANE b1 c1 b aaa M C A GAUGE PLANE SECTION W-W L1 W L W A1 A3 bbb C q (1.600) DETAIL Y MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 15 PACKAGE DIMENSIONS FC SUFFIX (44-LEAD QFN) PLASTIC PACKAGE CASE 1310-01 ISSUE D PIN 1 INDEX AREA 0.1 C 2X A 0.1 C 2X 9 M G 1.0 1.00 0.8 0.75 0.1 C 0.05 C (0.325) (0.65) DETAIL G VIEW ROTATED 90 CLOCKWISE 5 9 0.05 0.00 C SEATING PLANE M B 0.1 C A B 6.85 6.55 34 33 44 1 DETAIL M PIN 1 IDENTIFIER EXPOSED DIE ATTACH PAD 6.85 6.55 0.1 C A B 0.65 23 22 12 44X 40X 11 N 0.37 0.23 0.1 0.05 M M 44X 0.75 0.50 NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. CORNER CHAMFER MAY NOT BE PRESENT. DIMENSIONS OF OPTIONAL FEATURES ARE FOR REFERENCE ONLY. 5. COPLANARITY APPLIES TO LEADS, CORNER LEADS AND DIE ATTACH PAD. 6. FOR ANVIL SINGULATED QFN PACKAGES, MAXIMUM DRAFT ANGLE IS 12. VIEW M-M CAB C (45) (3.53) 0.60 0.24 0.60 0.24 CORNER CONFIGURATION OPTION 44X 0.065 0.015 (0.25) DETAIL N 4 DETAIL N 4 PREFERRED CORNER CONFIGURATION DETAIL T 3.4 3.3 0.475 0.425 BACKSIDE PIN 1 INDEX (90 ) 2X 0.39 0.31 R 0.25 0.15 PREFERRED BACKSIDE PIN 1 INDEX 2X 0.1 0.0 DETAIL M BACKSIDE PIN 1 INDEX OPTION DETAIL M PREFERRED BACKSIDE PIN1 INDEX DETAIL T 33887 16 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PACKAGE DIMENSIONS DWB SUFFIX (54-LEAD SOIC EXPOSED PAD) PLASTIC PACKAGE CASE 1377-01 ISSUE B 5 C 9 B 2.65 2.35 52X 10.3 7.6 7.4 1 54 0.65 PIN 1 INDEX 4 9 B B 18.0 17.8 C L 27 28 5.15 2X 27 TIPS A 54X SEATING PLANE NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 0.3 A B C A 0.10 A R0.08 MIN C A 8 0 C 0.25 GAUGE PLANE 0 MIN (1.43) 0.1 0.0 6.6 5.9 0.30 A B C 0.9 0.5 SECTION B-B (0.29) 0.30 0.25 6 0.38 0.22 0.13 M BASE METAL 4.8 4.3 0.30 A B C (0.25) PLATING A BC 8 ROTATED 90 CLOCKWISE SECTION A-A VIEW C-C MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 17 NOTES 33887 18 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA NOTES MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 19 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appl ication in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2002 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution: P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong. 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 MC33887/D |
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